Description of the Conventional Art
In conventional semiconductor systems, data is transferred in synchronization with a clock signal, and thus, synchronization between a clock signal and a data signal may be relatively important to the operation and/or function of the system. For example, in a system where a data value is determined at an edge of a clock signal, a phase and a frequency of the clock signal may be controlled so that the edge of the clock signal is located at the center of a data pulse. In synchronous circuits, a phenomenon in which the clock signal is transferred to respective components at different times, is referred to as clock skew. Clock skew may be caused by variations in transmission times for clock signals through a transmission line. Clock skew may also result from a delay during which a clock signal passes through an internal circuit of a chip.
A conventional semiconductor memory device provides an internal clock signal to a plurality of internal circuits using a clock driver having a higher or relatively high driving capability. However, if the plurality of internal circuits receive an external clock signal as an operation clock, clock skew between the external clock signal and the internal clock signal may be as much as a delay time during which the external clock signal passes through the clock driver, and an output of data may be delayed by as much as the delay time. A conventional delay-locked loop (DLL) may detect a phase difference between the external clock signal (or a reference signal) and the internal clock signal, and may compensate for the phase difference so that the internal clock signal is synchronized with the external clock signal.
A DLL may also change the phase of an internal clock signal periodically changed. In one example, a phase difference may be larger at an initial state of operation of a semiconductor device during which the DLL may compensate for the phase difference more coarsely. However, a phase of an output signal of the DLL may not be locked exactly with respect to a reference phase, and as a result, bang-bang jitter may occur. In at least one example, bang-bang jitter may result from the phase of the output signal of the DLL leading or lagging the phase of the reference signal (or the reference phase). If a coarse phase compensation of the output signal continues, bang-bang jitter may increase.
To suppress bang-bang jitter, the operation of a conventional DLL may be divided into two modes. For example, after the DLL operates for a first time interval (e.g., an initial locking mode), the DLL may coarsely compensate for a phase difference. After the first time interval (e.g., during a normal locking mode), the DLL may more finely compensate for the phase difference. In this example, to reduce locking time during the initial locking mode, a phase-update frequency of the DLL may be determined depending on a loop bandwidth of the DLL so that the phase-update frequency is closer to the loop bandwidth of the DLL. The phase-update frequency during the normal locking mode may be lower or substantially lower than the loop bandwidth of the DLL to reduce bang-bang jitter.
Although the operating frequency of a conventional semiconductor circuit may increase, the delay of a circuit receiving an internal clock signal may not decrease, and thus, phase difference may increase. Thus, updating a phase with a phase-update frequency closer to a loop bandwidth of a DLL during an initial locking mode may not be sufficient.
When a clock signal is out of a locked state or unlocked (e.g., when a lock drift occurs), during the normal locking mode, the conventional DLL may update a phase of the clock signal with a smaller or relatively small phase variation and a relatively low phase-update frequency. In this example, more clock cycles may be required to lock the clock signal with respect to the initial locking mode in the conventional DLL.
The DLL may fix a frequency of the clock signal to be less than a loop bandwidth of the DLL to suppress an incorrect phase update. Conventionally, operating frequencies of semiconductor devices increase relative to bandwidths. When a conventional semiconductor device starts to operate, a time during which the DLL locks the internal clock signal may be, for example, several tens of cycles, during which operating integrity of the semiconductor device may decrease.
In a conventional DLL, a phase-update frequency may be limited by the loop bandwidth of the DLL and extending the loop bandwidth of the DLL may be relatively difficult. On the one hand, when coarsely updating locking time may be shortened, but bang-bang jitter may increase. On the other hand, when finely updating, bang-bang jitter may be reduced, but the locking time may increase.